1. The Field of the Invention
The present invention relates to packaging and testing of microchips. More particularly, the present invention relates to methods of packaging a microchip for testing prior to mounting the microchip upon a circuit board. Additionally, the present invention relates to methods of testing a packaged microchip that has a tight lead pitch. In particular, the present invention relates to a method of packaging and testing a microchip with a tight lead pitch, wherein the testing method uses a probe and allows for removal of that portion of the lead which made contact with the probe, thus providing a shorter lead length.
2. The Relevant Technology
Microelectronic devices, such as semiconductor devices, are usually packaged on a lead frame structure to permit interconnection with a larger system. Often, the lead frame structures are connected to a printed circuit board (PCB) which, in turn, is connected to a larger electronic system such as a computer or other device.
After fabrication of a semiconductor integrated circuit, the integrated circuit is put through a die sort procedure. Each individual die is electrically tested for electrical performance and proper circuit functioning. During a die sort procedure, the integrated circuit is mounted on a vacuum chuck and aligned to thin electrical probes that contact each of the bonding pads on the die. The probes are connected to power supplies that test the circuit and record the results. Dies which do not pass the die sort are eliminated from the processing line. Dies which pass the die sort are singulated as chips and packaged into semiconductor device packages. The packaged semiconductor devices may then be re-tested prior to a final test and shipment.
As high integration and higher processing speeds of semiconductor devices have been improved, miniaturization and increased reliability of electronic devices has also been pursued. Along with miniaturization of circuits, miniaturization of chip packages has been a goal. That is, improvements have been necessary for coping with the needs for miniaturization of the packages, for achieving higher processing speeds of the semiconductor devices, and for achieving multiple-pin devices with increasingly narrower pitches.
In such packaging technology of semiconductor devices, chip mounting has progressed from through-hole mounting on a PCB to surface mounting on one side of the PCB. For example, in packaging plastic, especially in order to improve the mounting density upon a PCB, there has been proposed a vertical surface mounted package (VSMP). In the VSMP, a package is mounted perpendicularly on a surface of a PCB and, thus, the surface mounting technology can be applied to the chip package.
With packaging miniaturization, there occur accompanying problems. One problem is that when a VSMP is to be mounted on a board, mounting has to be substantially precise. Substantially imprecise mounting can cause leads to be bent, misaligned, or can cause solder bridges to form therebetween. Any significantly improper board mounting leads to device failure.
Testing of chip packages with tight-pitch leads is problematic because testing probes may have a characteristic diameter, such as a width, that may be greater than the width of a lead plus the space on either side thereof. Although testing probes of smaller dimensions are manufacturable, they add a significant increase to costs. Additionally, testing probes often tend to damage the portion of a lead upon which the probe makes contact. When such damage occurs, the lead must be reformed, commonly called "spanking" the lead. Although lead spanking or other reforming operations can in many cases reshape the lead after testing, it is an additional processing step and yield can decrease.
Lead length is also an important part of the overall semiconductor device. A reduced lead length allows for such advantages as a lower inductance, a higher speed, and a lower capacitance and a smaller package. As lead dimensions continue to decrease in size, fabrication of a robust lead that stands up to necessary testing procedures becomes a greater challenge.
What is needed in the art is a method of testing a chip in a chip package that allows for lower cost including larger diameter testing probes that have a characteristic dimension that is greater than the lead width. What is also needed in the art is a reduced lead length in a chip package that is produced without the processing of lead spanking or similar reforming operations. What is also needed in the art is a method of testing a chip in a package wherein incidental damage of any kind to the contacted portion of the lead is inconsequential to the final chip package to be used in the field.